The present invention relates to semiconductor memories having electrically erasable and programmable nonvolatile semiconductor memory cells. More specifically, the present invention is directed not only to a semiconductor memory for recording a plurality of pieces of bit data on a cell basis by setting one of four or more potential levels to each cell but also to an information storage device capable of including a semiconductor memory.
Keeping pace with the development of portable information devices, storage devices using a writable nonvolatile memory as a storage medium are rapidly gaining popularity in recent years.
However, the cost-per-unit-capacity of a storage device using a nonvolatile memory as a storage medium is higher than that of a storage device using a magnetic disk as a storage medium. Therefore, equipment requiring a large storage capacity often employs storage devices using a magnetic disk as a storage medium.
Under these circumstances, there has been a demand for an increased storage capacity in developing nonvolatile-memory-based storage devices.
Multilevel memory technology is a solution to meet this demand.
The multilevel memory technology involves a control over a potential of a floating gate provided in an electrically erasable and programmable nonvolatile semiconductor memory cell so that the potential belongs to one of a plurality of predetermined potential levels.
This technology also identifies a potential stored in a cell by checking which potential level such potential belongs to. Through these operations, a single cell is allowed to deal with multilevel data.
The aforementioned technology thus opens the way to the recording of data consisting of a plurality of bits in a cell unlike conventional technologies that allow only one-bit data to be recorded in a cell. As a result, large-capacity storage can be implemented.
In the multilevel memory technology, the operation of writing data to a cell is performed with considerations given to provide a margin between a desired potential level and a potential level adjacent to the desired potential level by controlling the setting of a potential to a floating gate more finely.
With respect to the reading of data written in a cell, techniques are disclosed in ISSCC95/Feb. 16, 1995/Digest of Technical Papers: Session 7 xe2x80x9cFlash Memoryxe2x80x9d TA 7.7 (pp. 132 to 133): A multilevel-Cell 32 Mb Flash Memory (INTEL Corporation), and JP-A-4-507320.
In the former technique, the potential level stored in a cell is identified from a plurality of predetermined potential levels through the operation of discriminating the potential stored in the cell (the operation of discriminating one of two levels) performed for a plurality of times. As a result of these operations, data consisting of a plurality of bits written in the cell is determined.
Let us take an example in which two-bit data is written to a single cell by setting the potential to be stored in the cell to one of four levels.
In this example, the four levels are grouped into two. A discriminating operation is performed to determine which group the potential stored in the cell belongs to.
Then, the group to which the potential stored in the cell belongs determined from the result of the discriminating operation is further divided into two subgroups, and another discriminating operation is performed to determine which subgroup the potential stored in the cell belongs to.
As a result of these operations, the level to which the potential stored in the cell belongs is identified from the predetermined four levels. Thus, the two-bit data written to the cell is determined.
On the other hand, in the latter technique, the level to which the potential stored in a cell belongs is identified from a plurality of predetermined levels using a plurality of discriminating means whose discriminating thresholds are different. Through this technique, data consisting of a plurality of bits written to the cell can be determined.
Let us take an example in which two-bit data is written to a single cell by setting the potential to be stored in the cell to one of four levels.
In this example, means for discriminating the first level and the second to fourth levels among the four levels are provided, and means for discriminating the first and second levels and the third and fourth levels are provided, and further means for discriminating the first to third levels and the fourth level are provided. By causing these discriminating means to perform their discriminating operations once, the level to which the potential stored in the cell belongs is identified from the four levels.
Through these operations, the two-bit data written to the cell is determined.
By the way, the read operation involved in the aforementioned multilevel memory technology addresses the following problems.
In the technique in which the level to which the potential stored in a cell belongs is identified from a plurality of predetermined levels through the potential discriminating operation performed for a plurality of times, data consisting of a plurality of bits is determined through the plurality of discriminating operations, and thus the read operation takes time.
The seriousness of this problem increases with increasing number of bits constituting the data to be stored in a single cell. Thus, this problem impairs the high-speed reading performance that is one of the advantages a storage device using a nonvolatile memory as a storage medium has over a storage device using a magnetic disk as a storage medium.
In the technique in which the level to which the potential stored in a cell belongs is identified from a plurality of predetermined levels using a plurality of discriminating means whose discriminating thresholds are different, a plurality of discriminating means must be provided, and thus the area of the chip is disadvantageously increased.
The seriousness of this problem also increases with increasing number of bits constituting the data to be stored in a single cell. That is, if two-bit data is to be stored in a single cell, three discriminating means are required per cell, which means that, if three-bit data is to be stored in a single cell, seven discriminating means are required per cell.
Such disadvantage, which is the increased chip area brought about by the increased number of peripheral circuits, does spoil the advantage, which is the increased storage capacity per array area given by the increased number of bits per cell.
The present invention has been made in view of the aforementioned circumstances. The object of the present invention is, therefore, to provide a semiconductor memory and an information storage device both capable of achieving multilevel memory technology without impairing data reading performance nor increasing chip area.
To achieve the above object, the present invention is applied to a semiconductor memory having an electrically erasable and programmable nonvolatile semiconductor memory cell, and such semiconductor memory includes:
means for setting a potential to the cell, the potential corresponding to a level indicated by a bit data string obtained by arranging a plurality of pieces of bit data to be stored in the cell in a predetermined order; and
means for discriminating or comparing the potential set to the cell by the potential setting means with a reference potential.
The discriminating means sequentially reads a plurality of pieces of one-bit data constituting the bit data string arranged in the predetermined order from a piece of one-bit data corresponding to a starting bit of the bit data string every time the discriminating means performs a discriminating operation with respect to the cell by setting the reference potential to a level, the level corresponding to a number of bits in the bit data string, a number of times of discriminating operations to be performed with respect to the cell and a result of the discriminating operation already performed with respect to the cell.
The discriminating means performs the discriminating operation, e.g., in the following procedure.
In a first discriminating operation with respect to the cell, the discriminating means discriminates the potential set to the cell by setting the reference potential to an intermediate level between a potential level corresponding to a minimum level possibly indicated by the bit data string when a value set to the starting bit of the bit data string is 1 and values set to other bits are unknown and a potential level corresponding to a maximum level possibly indicated by the bit data string when a value set to the starting bit of the bit data string is 0 and values set to other bits are unknown.
As a result of this operation, the starting bit data is read.
In a second discriminating operation with respect to the cell and onwards, the discriminating means discriminates the potential set to the cell by setting the reference potential to an intermediate level between a potential level corresponding to a minimum level possibly indicated by the bit data string when values set from the starting bit to a so-far-read bit of the bit data string are the respective read values and a value set to a next to-be-read bit is 1 and values set to other bits are unknown and a potential level corresponding to a maximum level possibly indicated by the bit data string when values set from the starting bit to the so-far-read bit of the bit data string are the respective read values and a value set to the next to-be-read bit is 0 and values set to other bits are unknown.
As a result of these operations, the to-be-read bit data is read.
By repeating the aforementioned discriminating operations sequentially, the pieces of bit data from the second to the final bit of the bit data string obtained by arranging the plurality of pieces of bit data in the predetermined order are sequentially read.
According to the semiconductor memory of the present invention having such structure, a plurality of pieces of one-bit data stored in a cell can be read on a one-bit data basis every time the discriminating means performs the discriminating operation with respect to the cell.
Therefore, multilevel memory technology can be achieved without impairing data reading performance nor increasing chip area due to an increased number of discriminating means.
In the semiconductor memory of the present invention, data is recorded and reproduced on a data block basis, a data block consisting of a plurality of its. Further, a plurality of cells are arranged in the semiconductor memory, each cell corresponding to the plurality of bits constituting the data block.
The potential setting means sets a potential to each of the plurality of cells, the potential corresponding to a level indicated by a bit data string obtained by arranging as many data blocks as a number of bits corresponding to the cell in a predetermined order.
A plurality of discriminating means are arranged, each discriminating means corresponding to each of the plurality of cells. The discriminating means may read a to-be-read data block from the plurality of cells by performing the operation of discriminating the potential of the corresponding cell for a number of times corresponding to a bit number from a first in the bit data string, the one-bit data constituting the to-be-read data block.
A file-based storage device usually records and reproduces data on a file basis, a file consisting of a plurality of sectors. That is, a plurality of sectors are recorded and read by a single access command operation. Further, the order in which the plurality of sectors are accessed is usually fixed.
When the semiconductor memory of the present invention is applied to a file-based storage device of the aforementioned type, each cell stores one bit from each of a plurality of sectors (data blocks) in a predetermined order. The potential to be set to each cell belongs to a level corresponding to a level indicated by a bit data string obtained by arranging a plurality of pieces of one-bit data respectively corresponding to the plurality of sectors in the order in which the plurality of sectors is accessed.
As a result of this arrangement, the sectors stored in a plurality of cells can be read in the order in which the sectors are accessed every time the discriminating means performs the discriminating operation.
That is, a piece of data can be retrieved from a sector without having to go through with all of the potential discriminating operation that is required to be performed for a plurality of times. Therefore, an access time similar to that required for a two-level memory can be achieved.
For example, a four-level memory cell can store two bits. A total of 4096 cells can store 1024 bytes, i.e., two sectors (one sector=512 bytes) in terms of the storage capacity of an ordinary hard disk drive (HDD).
Thus, the semiconductor memory of the present invention has 4096 cells, and the first to 4096th pieces of bit data in each of the two sectors are stored in the first to 4096th cells.
The potential of each cell is set to a level corresponding to a level indicated by a bit data string obtained by arranging two pieces of bit data to be stored in the cell in the order in which the two sectors are accessed.
As a result of this arrangement, the first discriminating operation performed by a discriminating means dedicated to each of the 4096 cells allows the previously accessed one of the two pieces of sector data to be retrieved, and the second discriminating operation allows the other, subsequently accessed one of the two pieces of sector data to be retrieved.
That is, the sector data can be read every time the discriminating means performs the discriminating operation, and thus an access time similar to that required for a two-level memory can be achieved.